Boundary Scan Testing
Boundary scan testing is described in many papers, including R. W. Bassett, M. E. Turner, J. H. Panner, P. S. Gillis, S. F. Oakland, and D. W. Stout, "Boundary Scan Design Principles for Efficient LSSD ASIC Testing," IBM Journal of Research and Development, Vol. 34, No. 2/3, March/May 1990, pp. 339-354.
Heretofore functional testing of printed circuit boards has been carried out by test fixtures that facilitated "bed of nails" contact of the individual integrated circuit leads. The development of high pin count devices and surface mount technology, with high populations of high I/O density, grid array components, on both sides of a card or board, has made bed of nails testing prohibitively expensive. To allow bed of nails testing, surface mount packages must either sacrifice their high I/O advantage and chip density, or even more complex and costly testing fixtures must be used.
Boundary scan testing provides an alternative to bed of nails testing. Boundary scan testing provides board signal node access while avoiding in circuit test fixturing. Boundary scan techniques replace the physical access points needed for in-circuit testing with equivalent logical access points. These equivalent logical access points are the boundary scan latches. The boundary scan latches correspond to the signal I/O pins of each component.
The board testing applications of boundary scan methodology have led to development of many boundary scan testing technologies, including Level Sensitive Scan Design devices and IEEE 1149.1 Standard devices.